LAYOUT DESIGN OF DIGITAL CIRCUITSSUBMITTED TO SUBMITTED BY
Mr. M.B. SRINIVAS; Mutta Praneeth Sri Sai;
BML MUNJAL UNIVERSITY; 1600411C204;
GURGOAN, HARYANA. CYIENT LIMITED;
Date of Submission: 29/06/2018.
LAYOUT DESIGN OF DIGITAL CIRCUITS
Mutta Praneeth Sri Sai
An open process design kit which supports a 150nm design flow is described which includes all the necessary design rules, models, Technology files, verification and extraction command checks, scripts and symbol libraries. Spice net lists, Stick Diagrams of inverter, nand, and nor gate is performed and the Verification -DESIGN RULE CHECKING COMMAND is performed for the layouts of inverter, nand, nor gate.
Now a days Electronics is playing a crucial role in everyday life. Along with the increase of electronics usage, the challenges offered by them is also increasing. Here it comes the major role of VLSI designer. Some circuits work for the first time, while some circuits take over a year and multiple design iterations to work properly and some circuits running red-hot requiring expensive cooling solutions while other circuits with similar performance, are running from small batteries in hand held gadgets. This is the only reason why do some companies make money with successful innovations and some companies doesn’t.
The best way to overcome the challenges is that Analysis and Design of system’s relevant electrical parameters. The deep submicron CMOS technologies have reduced the delays from device and gate level issues to interconnects and communication (metal wires) delays, where we currently do not have any design automation.
*The Two main concerns in VLSI design is that Speed and Area. With the scaling of Technology, effect of local interconnects is increasing.
“My Motivation for the work stems from the need for approaches to the design of VLSI devices which results in chips with lower power consumption and to avoid the parasitics that come into role while designing in layout.”
2. Hypothesis/Problem statement
Coming to the Layout design the major problems that displayed are clearance of Verification process which includes DRC CHECK -Design Rule Checking and LVS CHECK – Layout vs System, (here the system can be schematic). Going into background In Cadence the verification process takes place in Two steps. In the first step Cadence compare the layout design with the actual schematic which will be provided this verification is known as LVS. In The second step Cadence compare the layout with some specific design rules which are provided by the foundries this verification phase is known as DRC.
4067175541020000DRC determines the whether the physical layout satisfies a recommended parameter known as Design Rules. These design rules are specific to particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semi-conductor manufacturing process, to ensure that most of the parts work properly. The three basic DRC checks are listed below
1.WIDTH RULE: A width rule specifies the minimum width of any shape in the design. These rules will exist for each layer of semiconductor manufacturing process.
2.SPACING RULE: A spacing rule specifies the minimum distance between two adjacent objects. These rules will exist for each layer of semiconductor manufacturing process, with the lowest layers having the smallest rule.
3.ENCLOSURE RULE: The above two-layer rule specifies a relationship that must exist between two layers. For example, an enclosure rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer.
*Coming to LVS, LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. This netlist is compared by the “LVS” software against a similar schematic or circuit diagram’s netlist. LVS checking involves three major steps, namely- Extraction, Reduction and Comparison. In extraction phase the software extracts the information in the layout and in the reduction phase the software allots the numbers to layers and connections by making a spice net list. Once the net list is generated the software compares it with the actual spice net list which is provided as schematic.
The Method which is used for clearance of DRC errors is that while we are running QVI- (QUALCOMM VENDOR INTERFACE) by selecting the DRC check list box and the software starts checking the Design Rules. Then firstly the software checks will be initiated and later the process of checking begins started. Once the checks are done, if there are any errors present in the layout design a pop up raises up by telling that there are some errors with the layout. By selecting the option to VIEW the results. It shows us the what the errors that are in the layout and it suggests some parameters for the electronic components.
*By performing the QUALCOMM checks multiple times, we can rectify the DRC errors. Once the errors get reduced then the layout is subjected to again QVI- (QUALCOMM VENDOR INTERFACE) by marking the LVS check box instead of DRC then the software stars checking. Once the QUALCOMM checks get finished by selecting the option to view results it shows us either the layout is satisfying the Schematic. If not by checking the highlighting option it shows us where the errors are there. Then we can modify it.
*By performing the QUALCOMM checks multiple timed, we can rectify the errors by highlighting them. By running the QUALCOMM multiple times by noting down the minimum spacing that is required for the DRC verification we can reduce the DRC errors further.
*Coming to the progress saving, the Cyient Company allotted us a PATH in their LIBRARY FILES in which we can save our work and we can update the work after every successful check.
PATH NAME: ” /prj/analog/pmic5/encapa/work/.work-17/layout-SHARED/c-gsiddi”
*Once the Errors get cleaned the senior intern members or sometimes the CYIENT SEMICON-EMPLOYEES verifies the progress of the work and provides me some alternative way if the errors still continued after the DRC checks.
4. (Expected) Analysis and Results
*By Performing multiple times, the QUALCOMM checks, it allowed us to know what are the mistakes that are performed while designing the layout in Layout XL in Cadence. As per the method it is quite good enough because this method not only used for clearance of DRC but also a lot of experience how to handle the things that which where went wrong during DRC checks and also a lot of short cuts for designing the layout.
ANALYSIS: SCHEMATIC – INVERTER
right12065I have been assigned to generate the layouts for all the digital gates using mosfets. While coming to the inverter, In the first step a schematic view must be designed as per the circuit and later design in the layout must be performed. Once the designing is complete the verification must take place.
*it needs an PMOS and NMOS. In which source of pmos must be connected to Vdd and source of NMOS must be connected to Vss. While both the gate terminals of pmos and nmos must be connected and an input pin must be placed while both the drain terminals must be connected and the output pin must be placed on it.
Once the schematic is done we have to create a pmos and nmos for the layout.
Here it comes the analysis part, by performing the Qualcomm checks multiple times. It allowed me to clear all the required parameters like minimum width, spacing and enclosure separation.
*By performing the method multiple times, the dimensions get verified by DRC.
Once the DRC gets cleared for both the PMOS and NMOS. Then we should start up the wiring process and later sources are also connected.
Once the wiring is finished, we should run again the QUALCOMM checks for any error for LATCH UP, density, area errors.
Once the DRC gets finished then we have run the LVS and again if any errors it must be rectified. Once the DRC and LVS gets cleaned then our job is finished.
From the MULTIPLE QUALCOMM CHECKS:
TECHNOLOGY – TSMS 150 PM.
*Came to know about instance properties in 150 PM technology,
1. It must contain Minimum Area, Width, Spacing, Enclosure for the better performance of the circuit.
2. Instances must be placed as close by satisfying the design rules in such a way to avoid parasitics like diodes, capacitors etc.
because these unwanted parasitics may influence the function of the circuit.
1. Minimum Contact Spacing must be 0.21 u.
2.Space of contact on O.D region to poly must be 0.11u.
3. Minimum and Maximum Contact width must be 0.18u.
4. Minimum poly end cap must be 0.185u.
5. Minimum implant overlap over Active O.D must be 0.2u.
6. Minimum extension of m1 end of line region beyond CO region is 0.05 u.
7. Minimum separation between the implant and well must be 0.36u.
8. Separation between the poly end cap and the implant must be 0.1u.
9. Minimum separations between the metal and contacts are 0.05 and 0.005u.
10.Minimum metal to metal separation must be about 0.2u.
*Power Consumption decreases due to the reduction of Transistors.
*The packing density increases as less number of transistors.
*The Performance and Speed of the cell is also increases.
*Here, once the DRC checks of both the mos gets completed, then both the mos must be wired up and again QUALCOMM QVI checks must be initiated, if the errors are cleared up then the LVS check must be initiated. On a successful check of both the mos,
Then the inverter must be placed for fluid guard ring. Then the required layout design is obtained.
5. Related work primary protection circuit
right10795During the fabrication of CMOS using n-well process, we came to know about the Parasitics that came into role and how the Electronics testing industries test the electronic components. We came to know how to avoid latch up and ESD- Electro Static Discharge problems that occur and how to overcome them. This is the role in which the “CIRCUIT DESIGNER” must take care.
*In order to avoid the ESD an antiparallel diode, High reactive resistance and ground gated n-mos must be placed at the input side.
*To avoid the latch up problems, more substrate connections must be placed by increasing the more pick up points.
right1587500*Came to know about thyristor, The thyristor is a four-layered, three-terminal semiconductor device, with each layer consisting of alternately N-type or P-type material, for example P-N-P-N. The main terminals, labelled anode and cathode, are across all four layers. The control terminal, called the gate, is attached to p-type material near the cathode. The operation of a thyristor can be understood in terms of a pair of tightly coupled bipolar junction transistors, arranged to cause a self-latching action.
*Came to know about the PROCESS DESIGN KIT. This PDK files will be provided by the Foundry. It mainly contains four files namely:
1. TECHNOLOGY FILE commonly known as “TECH FILE”.
2. LAYER MAP FILE.
4. RULE FILE. (DRC, LVS, COMPARE, EXTRACT)
Coming to the Tech file, it provides us the information about what are the layers involved. In Layer map file, every layer will be allotted with some number when we are migrating from one technology to another technology it plays a crucial role. In Display files it contains the information about the displaying the colors for all different layers. In Rule File It comes the verification files like DRC, LVS and extraction and comparison for DF-II files from the layout.
The Industrial Training at CYIENT LIMITED, LANCO HILLS, HYDERABAD has given me an exposure to activities like Circuit Designing, Layout Designing, Circuit Programming, and physical verification Departments in CYIENT.
*CAD tools allows the freedom to VLSI Designers to focus on creativity with respect to process Technology.
*The development in the Design tools, collaborative design methods the role of human factors and integration factors in design technology marks the outline of Design methodologies.
*fundamentals of microelectronics, Art of Analog Layout- Alan Hastings.
*Design of Analog CMOS integrated circuits- Behzad Razavi.
*CMOS Analog circuit Design Second Edition – Fillipe.In, Holberg.
*CYIENT SEMICONDUCTORS- Cyient limited.